In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.
An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.
However, a characteristic of many current communication systems is that transmission information is collectively transmitted per variable-length packet or frame, as in the case of Ethernet (registered trademark). A problem with applying an LDPC code, which is a block code, to a system of this kind is, for example, how to make a fixed-length LDPC code block correspond to a variable-length Ethernet (registered trademark) frame. IEEE802.11n applies padding processing or puncturing processing to a transmission information sequence, and thereby adjusts the length of the transmission information sequence and the block length of the LDPC code. However, it is difficult to prevent the coding rate from being changed or a redundant sequence from being transmitted through padding or puncturing.
Studies are being carried out on LDPC-CC (Low-Density Parity Check Convolutional Codes) capable of performing encoding or decoding on an information sequence of an arbitrary length for LDPC code (hereinafter, LDPC-BC: Low-Density Parity Check Block Code) of such a block code (e.g. see Non-Patent Literature 8 and Non-Patent Literature 9).
LDPC-CC is a convolutional code defined by a low-density parity check matrix. For example, parity check matrix HT[0, n] of LDPC-CC having a coding rate of R=1/2 (=b/c) is shown in FIG. 1. Here, element h1(m)(t) of HT[0, n] takes zero or one. All elements other than h1(m)(t) are zeroes. M represents the LDPC-CC memory length, and n represents the length of an LDPC-CC codeword. As shown in FIG. 1, a characteristic of an LDPC-CC check matrix is that it is a parallelogram-shaped matrix in which ones are placed only in diagonal terms of the matrix and neighboring elements, and the bottom-left and top-right elements of the matrix are zero.
An LDPC-CC encoder defined by parity check matrix HT[0, n] where h1(0)(t)=1 and h2(0)(t)=1 is represented by FIG. 2. As shown in FIG. 2, an LDPC-CC encoder is formed with 2×(M+1) shift registers having a bit length of c and a mod 2 adder (exclusive OR operator). Thus, a feature of the LDPC-CC encoder is that it can be realized with a very simple circuit compared to a circuit that performs multiplication of a generator matrix or an LDPC-BC encoder that performs calculation based on a backward (forward) substitution method. Also, since the encoder in FIG. 2 is a convolutional code encoder, it is not necessary to divide an information sequence into fixed-length blocks when encoding, and an information sequence of any length can be encoded.
Patent Literature 1 describes an LDPC-CC generating method based on a parity check polynomial. In particular, Patent Literature 1 describes a method of generating an LDPC-CC using parity check polynomials having a time-varying period of two, a time-varying period of three, a time-varying period of four, and a time-varying period of a multiple of three.